Automatic identification procedures (Auto-ID) have become very popular in many service industries, purchasing and distribution logistics, industry, manufacturing companies and material flow systems. Automatic identification procedures exist to provide information about people, animals, goods and products in transit. RFID (Radio-Frequency Identification) technology has drawn a swirl of attention in the past few years as it helps identify objects and people in a fast, accurate and inexpensive way. It has been applied into many areas, including passports, transportation payment, product tracing, automotive as well as animal identification etc. Nowadays the applications of RFID are increasing rapidly, including supply chain management, access control to buildings, public transportation, open-air events, airport baggage and so on. To meet the market requirements, the preferred RFID system must exhibit features like low cost, long operation range and high data rate, requiring a small and low-voltage/lowpower integrated circuits.
This paper investigates a novel direct digital frequency synthesizer architecture, based on piecewise linear approximation with segments of nonuniform length.
The new approach allows reducing the total number of segments with respect to the well-known uniform segmentation. In this way the size of the coefficient ROM is also reduced with beneficial effects in terms of speed and power.
We show that the optimal nonuniform segmentation (that maximizes the spurious-free dynamic range for a given number of nonuniform segments) can be obtained as the solution of a mixed-integer linear programming problem.
Three simple, suboptimal, nonuniform segmentation schemes (which lend themselves to efficient hardware implementation) are proposed in this paper. We present also several design examples and VLSI implementation results, which demonstrate the effectiveness of the developed technique
Dual Data Rate SDRAM Controller
Abstract
Synchronous DRAM (SDRAM) has become a mainstream memory of choice in design due to its speed, burst access and pipeline features. For high-end applications using processors, the interface to the SDRAM is supported by the processor’s built-in peripheral module. However, for other applications, the system designer must design a controller to provide proper commands for DRAM initialization, read/write accesses and memory refresh. This SDRAM controller reference design, located between the SDRAM and the bus master, reduces the user’s effort to deal with the SDRAM command interface by
providing a simple generic system interface to the bus master
• Simplifies SDRAM command interface to standard system read/write interface.
• Internal state machine built for SDRAM power-on initialization.
• Read/write cycle access time optimized automatically according to the SDRAM timing spec and the mode it’s configured to.
• Dedicated auto-refresh request input and acknowledge output for SDRAM refresh.
• Easily configurable to support different CAS latency and burst length
